1. Field of the Invention
The present invention relates to a capacitor of a semiconductor memory device, and more particularly to a capacitor of a semiconductor memory device and a method for fabricating the capacitor of the semiconductor memory device which is not to be affected by misalignment of storage electrode and buried contact hole, but reinforces breakdown voltage of a dielectric layer formed between the storage electrode and a plate electrode.
2. Description of the Prior Art
In general, as the density of memory cells increases to improve integration degree of a semiconductor device like a DRAM, the size of memory cells have decreased according to the tendency of high integration. The reduction in the size of the memory cells directly results in reduction in capacitance of a capacitor. Thus, in order to achieve high integration of the semiconductor memory device, it is required that density of the memory cells should be increased along with the increase in capacitance of the capacitor. Since the increase in the capacitance of the capacitor improves the read-out capability of memory cells and reduces errors in the software system, a lot of research efforts have been concentrated on developing methods for increasing capacitance of the capacitor. Most of the research has focused on the structure of a storage electrode to make up the capacitor of the memory cells, such as a pin-shaped electrode made in Fujitsu Co., a box-structured electrode made in Toshiba Co., cylindrical-shaped electrode made in Mitsubishi Co. and the like. An attempt to increase the capacitance of the capacitor through an improvement made in the structure of the storage electrode has been made difficult due to a number of problems like limitations in designs, increase in process variations caused by complex fabricating processes, and the like. Therefore, in order to solve the aforementioned problems, it has been urgently demanded to develop a new method for fabricating the capacitor of the semiconductor memory device.
Recently, a lot of attention has been made to a capacitor over bit line (COB) structure of memory cells which are known to be suitable to 64 mega DRAM or 256 mega DRAM. In order to increase the density of the COB structure of memory cells, the pitch of the storage electrode has been reduced along with the reduction in the size of the buried contact hole. However, as there are limitations in the conventional fabricating processes to reduce the size of the buried contact hole, there has been provided a process of flowing a photo resist layer or an improvements in a method for etching an interlayer insulating layer. In other words, in case of the process of flowing a photo resist layer, a pattern of a photo resist layer having an aperture larger than the dimension of the buried contact hole to be formed, is formed on an interlayer insulating layer, and the pattern of the photo resist layer is used as a mask to form an etched groove by etching the interlayer insulating layer to a predetermined depth. Then, the pattern of the photo resist layer in an ADI (as development inspection) state is flowed in a predetermined width between a lower edge part and the lower middle part. Then the patterned flowed photo resist layer is used as a mask to etch the interlayer insulating layer exposed within the etched groove to expose a cell pad below. As a result, a desirably smaller buried contact hole is formed. However, after the patterned flowed photo resist layer is used as a mask for vertically etching the exposed portion of the interlayer insulating layer, a top critical dimension (CD) of the buried contact hole gets small but the middle and bottom CDs of the buried contact hole get large. Accordingly, the margin between the buried contact hole and the bit line gets smaller to deteriorate electrical insulation between the bit line and the storage electrode. Such may bring about defects in performances of the semiconductor memory device and reduction in the yield of products.
In order to solve the aforementioned problems, the pattern of the flowed photo resist layer is used as a mask to perform a slant etching process, instead of the vertical etching process, to the exposed portion of the interlayer insulating layer to expose the cell pad below. As a result, the top CD of the buried contact hole gets large, but the middle and bottom CDs of the buried contact hole get small. Accordingly, the margin between the buried contact hole and bit line gets larger, thereby improving the performance of the semiconductor memory device and increasing yield. However, it is very possible for the cell pad not to get exposed due to the smaller bottom CD, so that it gets more difficult to make an electrical connection between storage electrode and cell pad. Therefore, in order to enlarge the bottom CD of the buried contact hole, developments have been made to get the top CD as large as possible within the permitted limit of the fabricating processes.
A capacitor of the conventional type, as shown in FIG. 1, is constructed with a field oxide layer 11 at a field region of a P type silicon substrate 10, with the source S of N-type expansion region within the active region between the adjacent field oxide layer 11 regions. The polysilicon layer of cell pad 40 is above the source S and the interlayer insulating layer 50 having a planarized surface extends across the silicon substrate 10. The thickness of layer 50 is greater than the height of an upper surface of the cell pad 40. A bit line 60 is formed higher than the upper surface of the cell pad 40 in the interlayer insulating layer 50 between cell pads 40. A bar pattern 70 of the storage electrode is formed on the interlayer insulating layer 50 for making an electrical connection through the buried contact hole 53 with the cell pad 40. An Oxide/nitride/oxide (ONO)-structured dielectric layer 80, overlies the bar pattern 70 of the storage electrode, and then a plate electrode 90 is formed thereover, as shown. The bit line 60 is constructed with a polysilicon layer 61 and a silicide layer 63 formed on top of the polysilicon layer 61 to reduce resistance of the polysilicon layer 61.
In the memory cells thus constructed, a polysilicon layer acting as a conductive layer for the storage electrode is deposited on the interlayer insulating layer 50 having a buried contact hole 53. This exposes the upper surface of the cell pad 40 for filling in the buried contact hole 53 and provides a predetermined thickness suitable for formation of the bar pattern 70 of the storage electrode. In order to form the bar pattern 70 of the storage electrode, the unneeded part of the polysilicon layer is etched to expose the interlayer insulating layer 50 below. Afterwards, an additional over-etching process is performed to the polysilicon layer to secure electrical isolation between the bar pattern 70 of the storage electrode.
However, even if misalignment between the bar pattern of the storage electrode and the buried contact hole frequently happens, and the bar pattern 70 of the storage electrode often fails to completely cover the buried contact hole 53, but partially exposes the storage electrode in the buried contact hole 53. While the subsequent over-etching process is performed, an etched groove 71 is formed in a position of the storage electrode exposed in the buried contact hole 53. When it is deposited on the bar pattern 70, the dielectric layer 80 is not deposited uniformly in thickness within etched groove 71, thereby lowering the breakdown voltage and reducing the reliability of the capacitor.
Furthermore, the width of the storage electrode gets smaller at the upper part of the buried contact hole 53, lending the electrode mechanically weak. Therefore, in the course of the subsequent process steps for forming the dielectric layer 80 or the plate electrode 90, the physically narrow and thus somewhat fragile bar patterns 70 of the storage pattern collapse. Even if one or more bar patterns 70 of the storage electrode does not collapse, the buried contact resistance increases between the cell pad 40 and the bar pattern 70 of the storage electrode, thereby degrading the performances of the capacitor of the semiconductor memory device and, perhaps worse, reducing yield.
Therefore, it is an object of the present invention to provide a capacitor of a semiconductor memory device and a method for fabricating the capacitor, in spite of misalignment between storage electrode and buried contact hole, which can enhance the breakdown voltage of a dielectric layer formed between storage electrode and plate electrode.
It is another object of the present invention to provide a capacitor of a semiconductor memory device and a method for fabricating the capacitor that can prevent a bar pattern of a storage electrode from collapsing.
It is a further object of the present invention to provide a capacitor of a semiconductor memory device and a method for fabricating the capacitor that can reduce buried contact resistance between a bar pattern and a cell pad.
In order to accomplish the aforementioned object of the present invention, there is provided a capacitor of a semiconductor memory device comprises: a substrate having a cell pad exposed through a buried contact hole of an interlayer insulating layer; a storage electrode having a bar pattern formed on the interlayer insulating layer for making an electrical connection with the cell pad through the buried contact hole and conductive spacers formed on the side walls of the bar pattern; a dielectric layer formed on the storage electrode; and a plate electrode formed on the storage electrodes with the dielectric layer being inserted therein.
In order to accomplish the aforementioned object of the present invention, there is also provided a method for fabricating a capacitor of a semiconductor memory device comprising: preparing a substrate having a cell pad; forming an interlayer insulating layer having a buried contact hole to expose the cell pad over the substrate; forming a bar pattern of a storage electrode on the interlayer insulating layer for making an electrical connection with the cell pad through the buried contact hole; forming conductive spacers of storage electrode on side walls of the bar pattern; forming a dielectric layer on the storage electrode; and forming a plate electrode on all the storage electrodes with the dielectric layer being between the storage and plate electrodes.
Preferably, the spacer can be made of the same material as the bar pattern, a polysilicon layer, or another material. The width of the bottom of the spacer is made preferably over approximately 60 nm.
Therefore, even if an etched groove is formed at the bar pattern of storage electrode in the buried contact hole, the conductive spacers are formed on the side walls of the bar pattern of storage electrode to fill in the etched groove, thereby increasing breakdown voltage. In addition, the bar pattern does not collapse and the buried contact resistance does not get higher, consequently increasing yield.